Single instruction, multiple threads: Difference between revisions

Content deleted Content added
extra ref, hunting them down ...
Tags: Mobile edit Mobile web edit Advanced mobile edit
Description: added MIAOW GPU, about to add image. MIAOW is SIMT, implements Southern Islands AMDGPU ISA
Tags: Mobile edit Mobile web edit Advanced mobile edit
Line 52:
 
NVIDIA GPUs have a concept of the thread group called as "warp" composed of 32 hardware threads executed in lock-step. The equivalent in AMD GPUs is [[Graphics Core Next#Compute units|"wavefront"]], although it is composed of 64 hardware threads. In OpenCL, it is called as "sub-group" for the abstract term of warp and wavefront. CUDA also has the warp shuffle instructions which make parallel data exchange in the thread group faster,<ref>[https://developer.nvidia.com/blog/faster-parallel-reductions-kepler/ Faster Parallel Reductions on Kepler | NVIDIA Technical Blog]</ref> and OpenCL allows a similar feature support by an extension cl_khr_subgroups.<ref>[https://registry.khronos.org/OpenCL/sdk/3.0/docs/man/html/cl_khr_subgroups.html cl_khr_subgroups(3) Manual Page]</ref>
 
== Open hardware implementations ==
 
The MIAOW Project by the Vertical Research Group is an implementation of AMDGPU "Southern Islands".<ref> https://research.cs.wisc.edu/vertical/wiki/index.php/Main/Projects#miaow </ref>
 
== See also ==