Predication (computer architecture): Difference between revisions

Revision as of 05:35, 17 September 2024

Revision as of 07:13, 27 July 2025

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== SIMD, SIMT and vector predication ==

{{see also|Single instruction, multiple threads}}

Some [[SIMD within a register]] instruction sets, like AVX2, have the ability to use a logical [[Mask (computing)|mask]] to conditionally load/store values to memory, a parallel form of the conditional move, and may also apply individual mask bits to individual arithmetic units executing a parallel operation. One Thepredicate techniquemask [[Flynn'sbit taxonomy#Associative processor|is knownavailable infor Flynn'seach taxonomysub-word asof "associativethe processing"]]SWAR register.

This form of predication is also used in [[vector processors]] (at the sub-word, or element level) and [[single instruction, multiple threads]] GPU computing used in modern [[GPUs]], both to enable/disable individual Processing Elements ''and'', separately and further, to mask-out sub-words within any given PE's SWAR ALU. All the techniques, advantages and disadvantages of single scalar predication apply just as well to the parallel processing case.

==See also==