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→Pure (true) vector ISA: mention that n=0 is ok. explicitly Tags: Mobile edit Mobile web edit Advanced mobile edit |
→Pure (true) vector ISA: add additional IBM 370 example Tags: Mobile edit Mobile web edit Advanced mobile edit |
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Additionally, the number of elements going in to the function can start at zero. This sets the vector length to zero, which effectively disables all vector instructions, turning them into [[no-op]]s, at runtime. Thus, unlike non-predicated SIMD, even when there are no elements to process there is still no wasted cleanup code, or preamble: not even when n=0.
===== IBM 370 Vector facility =====
In the [[IBM 3090]] an additional benefit (further reduction in instruction count) was achieved.
<syntaxhighlight lang=gas>
LP: VSDS V0,F0,G1 # Compute S-A
VMD V0,V0,G2. # Compute A*(S-A)
VSTD V0,G3 # Store result in B
VLVCU G4 # Load VCT, update GR4
BC 3,LP # Branch back if VCT>0
</syntaxhighlight>
The {{code|VLVCU}} instruction would not only set the Vector Count Length ({{code|VCT}} but it would then subtract the new Vector Length from the Scalar register ''and'' update a Condition Code that the Branch could test. In effect {{code|VLVCU}} combined two (three including Condition Code setting) into one:
<syntaxhighlight lang=gas>
setvl G4, n # VL=G4=min(MVL, n)
sub n, G4 # n -= VL (G4), set CC
</syntaxhighlight>
=== Vector reduction example ===
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