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→IBM 370 Vector facility: clarify Libre-SOC assembler example Tags: Mobile edit Mobile web edit Advanced mobile edit |
→IBM 370 Vector facility: mention big saving compared to RVV Tags: Mobile edit Mobile web edit Advanced mobile edit |
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Post-update modes are added to Vectorised versions of Load-with-Update and Store-with-Update, again saving on the need for a separate instruction for address computation when the CPU's Load/Store internals has already done it. Note again that as with the IBM 370: the Vector y address is updated by the Store-with-Update, not a Load-with-Update.
The [[Power ISA]] CTR register is used for the total count instead of a scalar register, and the {{code|sv.bc/CTR}} instruction performs the reduction of CTR by the current Vector Length (VL) followed by testing CTR for being zero and branching if it is not
The approach is different but achieves the same end-result as the IBM 3090: a significant compacting of instructions that are already considered highly compact: [[RISC-V]] Vector DAXPY inner loop is 10 instructions,<ref>https://www.sigarch.org/simd-instructions-considered-harmful/</ref> where Libre-SOC and IBM 370 as shown above are both 6: a 40% reduction.
=== Vector reduction example ===
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