Revision as of 21:53, 3 August 2025 edit Lkcl (talk \| contribs) Extended confirmed users 3,004 edits →IBM 370 Vector facility: clarify example Tags: Mobile edit Mobile web edit Advanced mobile edit ← Previous edit		Revision as of 21:55, 3 August 2025 edit undo Lkcl (talk \| contribs) Extended confirmed users 3,004 edits →IBM 370 Vector facility: syntax Tags: Mobile edit Mobile web edit Advanced mobile edit Next edit →
Line 399: The [[Power ISA]] CTR register is used for the total count instead of a scalar register, and the {{code\|sv.bc/CTR}} instruction performs the reduction of CTR by the current Vector Length (VL) followed by testing CTR for being zero and branching if it is not. The approach is different but achieves the same end-result as the IBM 3090: a significant compacting of instructions that are already considered highly compact:.<ref>https://www.sigarch.org/simd-instructions-considered-harmful/</ref> a [[RISC-V]] Vector DAXPY inner loop example is 10 instructions, where Libre-SOC and IBM 370 as shown above are both 6: a 40% reduction. === Vector reduction example ===

Vector processor: Difference between revisions