Instruction set architecture: Difference between revisions

Revision as of 16:41, 11 August 2025

Revision as of 20:23, 11 August 2025

Line 130:

==={{Anchor|REGISTER-PRESSURE}}Register pressure===

''Register pressure'' measures the availability of free registers at any point in time during the program execution. Register pressure is high when a large number of the available registers are in use;. thusThus, the higher the register pressure, the more often the register contents must be [[register spilling|spilled]] into cache or memory, which, given thetheir slower speed of memory, exacts a heavy price. Increasing the number of registers in an architecture decreases register pressure but increases the cost.<ref>{{cite book |last=Page |first=Daniel |title=A Practical Introduction to Computer Architecture |chapter=11. Compilers |year=2009 |publisher=Springer |isbn=978-1-84882-255-9 |page=464|bibcode=2009pica.book.....P }}</ref>

While embedded instruction sets such as [[ARM Thumb|Thumb]] suffer from extremely high register pressure because they have small register sets, general-purpose RISC ISAs like [[MIPS architecture|MIPS]] and [[DEC Alpha|Alpha]] enjoy low register pressure. CISC ISAs like x86-64 offer low register pressure despite having smaller register sets. This is due to the many addressing modes and optimizations (such as sub-register addressing, memory operands in ALU instructions, absolute addressing, PC-relative addressing, and register-to-register spills) that CISC ISAs offer.<ref>{{cite conference |last1=Venkat |first1=Ashish |last2=Tullsen |first2=Dean M. |title=Harnessing ISA Diversity: Design of a Heterogeneous-ISA Chip Multiprocessor |year=2014 |conference=41st Annual International Symposium on Computer Architecture |url=http://dl.acm.org/citation.cfm?id=2665692}}</ref>