Single instruction, multiple threads: Difference between revisions

Revision as of 08:41, 12 August 2025

Revision as of 08:42, 12 August 2025

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{{Short description|Parallel Execution model which works simultaneously on arrays of several numbers}}

{{About|Processors designed to simultaneously '''and synchronously''' perform the exact same operation on a massive Vectors (Arrays)|SIMD instructions present in some general-purpose computers|[[SIMD]]Flynn's taxonomy#Array processor|'''Sequential''' processing of arrays|Flynn's taxonomy#Array processor|Vector processor}}

'''Single instruction, multiple threads''' ('''SIMT''') is an execution model used in [[parallel computing]] where a single central "Control Unit" broadcasts an instruction to multiple "Processing Units" for them to all ''optionally'' perform simultaneous synchronous and fully-independent parallel execution of that one instruction. Each PU has its own independent data and address registers, its own independent Memory, but no PU in the array has a [[Program counter]]. In [[Flynn's taxonomy|Flynn's 1972 taxonomy]] this arrangement is a variation of [[SIMD]] termed an '''array processor'''.