Bit manipulation instructions: Difference between revisions

Revision as of 18:49, 12 August 2025

Revision as of 18:53, 12 August 2025

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** Population count {{code|popcnt}}

** Bit extract/bit deposit {{code|pext}}/{{code|pdep}}

** Bit test {{code|PTEST}} given two inputs does a {{code|AND}} and{{code|ANDN}} operation between them, and sets two separate CPU branch registers on wetherwhether the results are 0. This can be used to test if all masked bits are zero, all masked bits are set, or a mix.

* The [[AVX-512#Bitwise ternary logic|AVX-512 ternary]] extension includes a [[Bitwise ternary logic instruction]], {{code|vpternlog}}. Also noteworthy is a conflict detection instruction. [[AVX-512#Conflict detection|<code>VPCONFLICTD</code>]]

* Also present in the AVX/[[AVX-512]] [[GFNI instruction set|GFNI subset]] is bit-matrix affine transformation and its inverse: {{code|GF2P8AFFINEQB}} is effectively an 8x8 bit-matrix multiply in the [[Galois field]] GF(2^8).<ref>{{cite web | title=GF2P8AFFINEQB — Galois Field Affine Transformation | url=https://www.felixcloutier.com/x86/gf2p8affineqb }}</ref>