Clock ___domain crossing

In digital electronic design a clock ___domain crossing (CDC), or simply clock crossing, is the traversal of a signal in a synchronous digital circuit from one clock ___domain into another. If a signal does not assert long enough and is not registered, it may appear asynchronous on the incoming clock boundary.^[1]

A synchronous system is composed of a single electronic oscillator that generates a clock signal, and its clock ___domain—the memory elements directly clocked by that signal from that oscillator, and the combinational logic attached to the outputs of those memory elements.

Because of speed-of-light delays, timing skew, etc., the size of a clock ___domain in such a synchronous system is inversely proportional to the frequency of the clock.^[2] In early computers, typically all the digital logic ran in a single clock ___domain. Because of transmission line loss and distortion it is difficult to carry digital signals above 66 MHz on standard PCB traces (the clock signal is the highest frequency in a synchronous digital system), CPUs that run faster than that speed invariably are single-chip CPUs with a phase-locked loop (PLL) or other on-chip oscillator, keeping the fastest signals on-chip. At first, each CPU chip ran in its own single clock ___domain, and the rest of the digital logic of the computer ran in another slower clock ___domain. A few modern CPUs have such a high speed clock, that designers are forced to create several different clock domains on a single CPU chip.^{[when?][which?]}

Different clock domains have clocks which have a different frequency, a different phase (due to either differing clock latency or a different clock source), or both.^[3] Either way the relationship between the clock edges in the two domains cannot be relied upon.

Synchronizing a single bit signal to a clock ___domain with a higher frequency can be accomplished by registering the signal through a flip-flop that is clocked by the source ___domain, thus holding the signal long enough to be detected by the higher frequency clocked destination ___domain.

CDC metastability issues can occur between asynchronous clock domains; this is in contrast to reset ___domain crossing metastability, which can occur between synchronous & asynchronous clock domains.^[4] To avoid issues with CDC metastability in the destination clock ___domain, a minimum of 2 stages of re-synchronization flip-flops are included in the destination ___domain. Synchronizing a single bit signal traversing into clock ___domain with a slower frequency is more cumbersome. This typically requires a register in each clock ___domain with a form of feedback from the destination ___domain to the source ___domain, indicating that the signal was detected.^[5] Other potential clock ___domain crossing design errors include glitches and data loss.^[6]

In some cases, clock gating can result in two clock domains where the "slower" ___domain changes from one second to the next.

See also

• Crosstalk (electronics)
• Metastability in electronics
• Globally asynchronous, locally synchronous
• Source-synchronous
• Gray code
• asynchronous array of simple processors
• The topic is duplicated in Flip-flop (electronics) § Timing considerations

References

1. Parker, Roy H. (2004-06-02). "Caution: Clock Crossing – A prescription for uncontaminated data across clock domains". Chip Design Magazine – Tools, Technologies & Methodologies. No. 5. Extension Media, Inc. Article 32. Archived from the original on 2019-03-27.
2. Seitz, Charles L. (December 1979) [1978-07-23]. "Chapter 7: System Timing" (PDF). In Mead, Carver; Conway, Lynn (eds.). Introduction to VLSI Design (1 ed.). Addison Wesley. ISBN 0-20104358-0. ISBN 978-0-20104358-7. Archived (PDF) from the original on 2020-06-19. Retrieved 2020-08-06. (46 pages) (NB. Cf. isochronous region.)
3. Asic World: Interfacing Two Clock Domains
4. BTV: Reset Domain Crossing Sign-Off Fundamentals
5. Stein, Mike (2003-07-24). "Crossing the abyss: asynchronous signals in a synchronous world – as digital design becomes increasingly sophisticated, circuits with multiple clocks must reliably communicate with each other" (PDF). EDN. Paradigm Works, Andover, Massachusetts, USA. pp. 59–60, 62, 64, 66, 68–69. Archived (PDF) from the original on 2016-03-04. Retrieved 2020-08-06. (7 pages)
6. SemiEngineering: Clock Domain Crossing (CDC)

Further reading

• Patil, Girish (2004). "Clock ___domain crossing - Closing the loop on clock ___domain functional implementation problems" (PDF). Cadence Design Systems. Archived from the original (PDF) on 2007-01-25. (10 pages)
• Yeung, Ping (2007). "Five Steps to Quality CDC Verification" (PDF). eeNews Europe. Mentor Graphics. (17 pages)
• Athanas, Peter M. (2015). "1: Clock Domain Crossing". LEDA. Course 4514. Blacksburg, Virginia, USA: Bradley Department of Electrical and Computer Engineering, Virginia Tech. Archived from the original on 2015-05-11. Retrieved 2020-08-06.